Test Case : FIFO : Cycle-accurate bus-protocol
          : RPC mechanism with blocking read and write
		   using sc_async_tprocess
    
  
FIFO illustrates blocking RPC model for blocking write and read in a FIFO 
communication link. A producer process produces data items (integers in this 
example) and sends it through the FIFO link to the consumer. The producer runs
at a higher speed than the consumer process such that the FIFO buffer will get 
full after some time. This will block the producer process since it will not be 
able to write into the FIFO buffer. As soon as the consumer removes an item 
from the FIFO buffer, the producer will be unblocked and write another item into
the buffer.


           clk1                                          clk2   
            |                                             |
      ______V______        __________________        _____V______
     |             |      |                  |      |            |
     |             |  BW  |bWrite      bRead |  BR  |            |
     |   PRODUCER  |------|       FIFO       |------|  CONSUMER  |
     |             |      |                  |      |            |
     |_____________|      |__________________|      |____________|


Full-handshake protocol is used between the producer/ consumer threads and the 
FIFO. Enable-handshake protocl would not work here since the FIFO is blocking. 

The producer and consumer are implemented as clocked SC_THREAD process to allow
the two processes to run at different 'speeds'. Producer is sensitive to the 
clock. Producer has a sc_outmaster port with fullhandshake protocol, through 
which it invokes the blockingWrite() slave process in the FIFO. The 
blockingWrite() blocks when the buffer is full. The state of the buffer is 
tested on every sensitive clock edge of the producer clock. Consumer is 
sensitive to a different clock. Consumer has an sc_inmaster port through which 
it invokes the blockingRead() slave process in the FIFO. The blockingRead() 
blocks when the buffer is empty. The state of the buffer is tested on every 
sensitive clock edge of the consumer clock. For the shake of brevity, the buffer
class is not shown in the code below. The buffer has intentionally a 'full' and
an 'empty' signal to keep the bufer's state such that the buffer has a 
deterministic behavior, i.e. its behavior does not depend on which of 
blockingWrite() and blockingRead(), process checks first the state of the buffer
in a given delta cycle.


